1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a method of forming a MOS transistor on a semiconductor wafer.
2. Description of the Prior Art
A metal-oxide semiconductor (MOS) is a very common electrical device in integrated circuits. A gate, a source, and a drain together comprise the MOS transistor to form a unit with four nodes. By utilizing channel effects generated by the gate of the MOS under different gate voltages, the MOS is often made to function as a digital solid switch. With the increasing sophistication of production technology, the size of these units has become smaller and smaller, and consequently so, too, has their channel length. However, when the channel length is too short, a short channel effect can occur that affects the switching function of the gate.
A lightly doped drain implantation process is currently employed to resolve the short channel effect. Please refer to FIG. 1 to FIG. 5. FIG. 1 to FIG. 5 are cross-sectional diagrams of the prior art method of forming a MOS transistor. As shown in FIG. 1, the MOS transistor is formed on a semiconductor wafer 10. The semiconductor wafer 10 comprises a silicon substrate 12, and a dielectric layer 14 installed on the silicon substrate 12.
As shown in FIG. 2, during the formation of the MOS transistor, a gate 16 is formed on a predetermined region of the dielectric layer 14. The dielectric layer 14 beyond the predetermined region is removed down to the silicon substrate 12. As shown in FIG. 3, a first ion implantation process 18 is performed to form two doped regions on the silicon substrate 12 adjacent to two opposite sides of the gate. Each doped region functions as a lightly doped drain (LDD) 22 of the MOS transistor.
As shown in FIG. 4, two spacers 24 made of insulating material are formed on opposite sides of the gate 16. As shown in FIG. 5, a second ion implantation process is performed to form two doped regions on the silicon substrate 12 adjacent to the spacers 24. The two doped regions function as a source 27 and a drain 28 of the MOS transistor.
Please refer to FIG. 6. FIG.6 is a cross-sectional diagram of the MOS transistor after a self-alignment silicide process has been performed. The self-alignment silicide (salicide) process is performed to reduce the contact resistance of each silicon surface. As shown in FIG. 6, after the self-alignment silicide process, a silicide layer 32 is formed on the surface of the gate 16, the source 27 and the drain 28 of the MOS transistor.
The length of the spacer 24 on two opposite sides of the gate 16 decides the final length of the LDD 22. In order to keep the junction deep between the source 27 and the drain 28, the width of the spacer 24 is always about 800.about.1500 .ANG.. This prevents the device driving current of the unit from being affected by thermal treatment processes or the source and drain implantation process, and also avoids device shorting effects. However, with the reduction of the unit size, the LDD 22 also becomes smaller and thinner. This lower implantation energy of the LDD greatly increases the extension external resistance of the LDD 22, and decreases the extension coupling between the gate and the LDD 22.